Congestion Driven Buffer Planning for X-Architecture

With recent advance of VLSI design, interconnect delay plays dominant role in the chip performance. X-architecture, which is based on pervasive use of 0-degree, 45-degree, 90-degree and 135-degree-oriented wiring, has been proposed to achieve high-performance by reducing wire length and via count. In this paper, a buffer planning algorithm at floorplanning stage for X-arch is proposed. Firstly, the concept of feasible region (FR) is extended to X-arch feasible region (XFR) by which buffer regions for a net in X-arch can be determined. Then, a new buffer insertion algorithm using shortest-path model is applied with consideration of X-arch routing congestion. At last, dead space redistribution is performed to optimize timing performance and congestion