Applying a redundancy scheme to address post-assembly yield loss in 3D FPGAs

Advancement in 3D integration by die and wafer level stacking has enabled a wide variety of applications. There is an increasing demand for higher capacity and functionality in Field Programmable Gate Arrays (FPGAs) to improve performance, overall power consumption and form factor. FPGA capacity can be dramatically increased by stacking multiple smaller FPGA die on a passive interposer. The required interconnect between dies is achieved with densely packed inter-die drivers and minimum size μ-bumps. Aggressive sizing of interconnect structures poses a challenge to control post-assembly yield loss due to μ-bump or interposer defects. This paper proposes a redundancy scheme and repair technology to address this issue, significantly reducing 3D FPGA post-assembly yield loss.