Title :
Chip Package Interaction with fine pitch Cu pillar bump using mass reflow and thermal compression bonding assembly process for 20nm/16nm and beyond
Author :
Zhao, Lu ; Bao, Andy ; YangYang Sun ; Chun-Jen Chen ; Tsai, S. ; Lee, Kahyun ; Xuefeng Zhang ; Perry, Dan ; Kalleberg, Tor ; Han, Myungjin ; Bezuk, Steve ; Yeap, Geoffrey
Author_Institution :
Qualcomm Technol. Inc., San Diego, CA, USA
Abstract :
This paper summarizes key learnings on 20/16nm CPI (Chip-Package-Interaction) challenges at 100um pitch and below to support ever increasing performance/cost/form factor demands for high performance mobile SoCs. CPI solutions for two types of Cu pillar interconnects using mass reflow and thermal compression type assembly process respectively are studied in technology development/production, and separate bump cell structures are proposed.
Keywords :
bonding processes; chip scale packaging; copper; integrated circuit interconnections; system-on-chip; CPI challenges; CPI solutions; Cu; Cu pillar interconnects; bump cell structures; chip-package-interaction challenges; high performance mobile SoC; mass reflow assembly process; performance-cost-form factor demands; size 100 mum; size 16 nm; size 20 nm; thermal compression bonding assembly process; thermal compression type assembly process; Assembly; Bonding; Delamination; Metals; Reliability; Stress; Substrates;
Conference_Titel :
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3331-0
DOI :
10.1109/VLSIT.2014.6894412
