An Efficient Hardware Architecture Design for H.264/AVC INTRA 4X4 Algorithm

In this work, we present architecture for real-time implementation of INTRA 4 times 4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4 times 4 is composed by intra prediction 4 times 4, integer transform 4 times 4, quantization 4 times 4, inverse integer transform 4 times 4, inverse quantization 4 times 4. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 160 MHz in an ALTERA Stratix II FPGA. This architecture can process one macroblock (MB) for 432 clock cycles.