DocumentCode
2304879
Title
A 20-GSample/s (10 GHz × 2 clocks) burst-mode CDR based on injection-locking and space sampling for access networks
Author
Shastri, Bhavin J. ; Prucnal, Paul R. ; Plant, David V.
Author_Institution
Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA
fYear
2012
fDate
23-27 Sept. 2012
Firstpage
717
Lastpage
718
Abstract
We demonstrate a novel 20-GSample/s burst-mode CDR circuit featuring instantaneous (0-bit) phase acquisition with BER<;10-10 for any phase step (2π rad) between successive bursts. Our design incorporates injection-locking and space sampling for clock phase recovery/alignment.
Keywords
clock and data recovery circuits; error statistics; optical fibre subscriber loops; access networks; bit error rate; burst mode CDR; clock phase alignment; clock phase recovery; frequency 10 GHz; injection locking; passive optical networks; phase acquisition; space sampling; Bit error rate; Clocks; Educational institutions; Jitter; Logic gates; Photonics; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Photonics Conference (IPC), 2012 IEEE
Conference_Location
Burlingame, CA
Print_ISBN
978-1-4577-0731-5
Type
conf
DOI
10.1109/IPCon.2012.6358823
Filename
6358823
Link To Document