Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays

Author

Hong-Yu Chen ; Bin Gao ; Haitong Li ; Rui Liu ; Peng Huang ; Zhe Chen ; Bing Chen ; Feifei Zhang ; Liang Zhao ; Zizhen Jiang ; Lifeng Liu ; Xiaoyan Liu ; Jinfeng Kang ; Shimeng Yu ; Nishi, Yoshio ; Wong, H.-S Philip

Author_Institution

Peking Univ., Beijing, China

fYear

2014

fDate

9-12 June 2014

Firstpage

1

Lastpage

2

Abstract

3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3D array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.

Keywords

integrated circuit reliability; random-access storage; three-dimensional integrated circuits; 2D array; 3D vertical RRAM arrays; DSB scheme; array-level evaluation; cell-location-dependent write-access; conducting single-device measurements; disturbance issues; double-sided bias scheme; reliability issues; selected cells; towards high-speed; unselected cells; write latency reduction; write-disturb tolerance improvement; Analytical models; Face; Pulse measurements; SPICE; Switches; Three-dimensional displays; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4799-3331-0

Type

conf

DOI

10.1109/VLSIT.2014.6894434

Filename

6894434