High density integrated circuit design: simultaneous switching ground/power noises calculation for pin grid array packages

The author presents basic electrical models to calculate equivalent inductances (noises) for a 179 pin grid array package as a function of ground/power/signals pin organizations. A full experimental inductances measurement based on time domain reflectometry and frequency method is also presented. A specific test vehicle was elaborated to avoid fixturing noise. Calculated and measured signal effective inductance values are compared. Each integrated circuit logic family has a specific switching point. Thus, adequate ground/power/signal organization depends on the technology used. For some logic families like TTL (transistor transistor logic) and DCFL in silicon and GaAs technologies, the switching point near the ground voltage indicates that the critical path is ground. On other hand, the internal switching current becomes comparable to the input buffers (30-50 mA/ns). Thus, the ground/signal/power organization of output buffers must take into account the internal logic I/O´s (input/outputs). The noises are as function of the number of IO buffers and internal logic IO gates