Title :
Dual-Level Metal (DLM) method for fabricating thin film wiring structures
Author :
Ray, S. ; Berger, D. ; Czornyj, G. ; Kumar, A. ; Tummala, R.
Author_Institution :
Technol. Products, IBM Corp., Hopewell Junction, NY, USA
Abstract :
This paper describes a fabrication method for multilevel, thin film wiring in which each wiring level and a solid via or stud to the level below, are formed as one integral unit. The processing scheme described makes use of a photosensitive polyimide (PSPI) for defining the wiring channels and a non-photosensitive polyimide for the vias. The via opening in the non-photosensitive polyimide is formed by laser ablation while the wiring channels are formed in the PSPI layer by photolithography. The via hole and the channels in the PSPI are filled in the same metallization step consisting of electroplating copper over a sputtered seed layer. The wiring pattern is finally delineated when a planarization step removes the excess plated copper. This processing method, which we refer to as the Dual Layer Metallization (DLM) method, is found to be very economical, in terms of the number of process steps involved, for forming multilevel, polyimide-copper wiring structures
Keywords :
electroplating; integrated circuit technology; laser ablation; metallisation; packaging; photolithography; polymer films; wiring; dual-level metal method; electroplating; high density interconnection; laser ablation; multichip packages; multilevel wiring; nonphotosensitive polyimide; photolithography; photosensitive polyimide; planarization step; polyimide-copper wiring structures; solid via; sputtered seed layer; thin film wiring structures; wiring channel; Copper; Fabrication; Laser ablation; Lithography; Metallization; Planarization; Polyimides; Solids; Transistors; Wiring;
Conference_Titel :
Electronic Components and Technology Conference, 1993. Proceedings., 43rd
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-0794-1
DOI :
10.1109/ECTC.1993.346793