DocumentCode
2307499
Title
Design of efficient radix-8 butterfly PEs for VLSI
Author
Widhe, T. ; Melander, J. ; Wanhammar, L.
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Sweden
Volume
3
fYear
1997
fDate
9-12 Jun 1997
Firstpage
2084
Abstract
In this paper we discuss various aspects of VLSI implementation of radix-8 Sande-Tukey butterfly PEs. The Sande-Tukey algorithm is investigated to find regularities and simplifications. We argue that a bit-serial implementation of the butterfly PEs will be advantageous from an area point of view under most circumstances. The ideas are supported by a design example, a radix-8 butterfly PE that will be used in a 512 point FFT/IFFT processor aimed at OFDM applications
Keywords
CMOS digital integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; pipeline processing; DSP chip; FFT/IFFT processor; OFDM applications; Sande-Tukey algorithm; Sande-Tukey butterfly PEs; VLSI implementation; bit-serial implementation; radix-8 butterfly processing elements; Batteries; Digital signal processing; Fast Fourier transforms; Hardware; Memory architecture; OFDM; Signal design; Signal processing algorithms; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN
0-7803-3583-X
Type
conf
DOI
10.1109/ISCAS.1997.621567
Filename
621567
Link To Document