A Linear Voltage Regulator for PLL in SOC Application

Author

Jia, Chen ; Qin, Bo ; Chen, Zhiliang

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing

fYear

2006

fDate

22-24 Sept. 2006

Firstpage

1

Lastpage

4

Abstract

In modern integrated circuit design, analog parts and digital parts are designed on a single chip. Many papers show that supply noises coupling from digital parts influence the performance of analog parts greatly. This paper presents a design to implement a linear voltage regulator with operational amplifiers for PLL in mixed signal integrated circuits, whose output voltage is proportional to bandgap reference. This circuit is designed in SMIC 0.18 mum CMOS process. The output voltage of the regulator can be stable when 1) power supply changes from 3.1 V to 3.5 V, and verse; 2) output current varies in the range from 15 mA to 300 muA. Its power supply noise rejection(PSNR) is less than -70 dB when frequency is below 1 KHz. The current consumption of this linear voltage regulator is about 1.7 mA

Keywords

CMOS integrated circuits; mixed analogue-digital integrated circuits; operational amplifiers; phase locked loops; system-on-chip; voltage regulators; CMOS process; PLL; SOC; linear voltage regulator; mixed signal integrated circuit design; operational amplifiers; power supply noise rejection; Coupling circuits; Integrated circuit noise; Integrated circuit synthesis; Mixed analog digital integrated circuits; Operational amplifiers; Phase locked loops; Power supplies; Regulators; Signal design; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications, Networking and Mobile Computing, 2006. WiCOM 2006.International Conference on

Conference_Location

Wuhan

Print_ISBN

1-4244-0517-3

Type

conf

DOI

10.1109/WiCOM.2006.164

Filename

4149341