Mixed behavior-logic simulation in a hardware accelerator

A mixed-mode hardware simulator that combines logic and behavioral model evaluation capabilities without the addition of a coprocessor or any hardware is described. This simulator is implemented in the MARS (microprogrammable accelerator for rapid simulation) multicomputer system. The MARS hardware simulator is a mixed-mode logic-behavior-memory simulator applicable to the design of both custom and semicustom integrated circuits. It is particularly suited for the simulation of ASICs (application specific integrated circuits). The major benefit of this simulator is the reduced element count compared to simulators that make use of four-input primitives. Most of the reduction is due to flip-flops, buffers and high-speed combinational elements. The evaluation time per element will be increased by 20-50%, depending on the element type. However, the total simulation time will be shorter because of the reduced element count. Race analysis, setup, and hold time violations can be detected by monitoring the clock and data inputs during simulation and postprocessing the simulation results