Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains

This paper presents a clock control architecture for designs with multiple clock domains, and a novel mix of existing ATPG techniques as well as novel ATPG enhancements. The combination of the ATPG techniques and the clock control hardware lowers the number of test patterns in a fully automated flow, while maintaining the high coverage that is required nowadays by production test. Experimental results are shown for two industrial designs.