Bandwidth extension of analog multiplier using dynamic threshold MOS transistor

This paper presents an attractive approach for bandwidth extension of a four quadrant CMOS analog multiplier. The proposed approach is based on using dynamic threshold MOS transistor (DTMOS) which is an effective technique that achieves supply voltage reduction with a simultaneous increase in the overall transconductance of the MOS transistor. The proposed multiplier can operate at very high frequencies at low supply voltage of 0.6V without any distortion. The proposed approach increases the bandwidth of multiplier by 4.6GHz at unity gain. This multiplier is simulated at 180nm technology and has high gain in comparison to previous reported circuit. The proposed approach optimizes multiplier bandwidth and thus more suitable for high frequency and low voltage applications.