Title :
Dynamic channel allocation for higher EDT compression in SoC designs
Author :
Kassab, M. ; Mrugalski, G. ; Mukherjee, N. ; Rajski, J. ; Janicki, J. ; Tyszer, J.
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
Abstract :
The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously.
Keywords :
data compression; system-on-chip; EDT compression; EDT-based compression; SoC designs; SoC devices; dynamic channel allocation; non-isolated cores; preemptive test application scheme; system-on-chip; test scheduling algorithm;
Conference_Titel :
Test Conference (ITC), 2010 IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-7206-2
DOI :
10.1109/TEST.2010.5699227
