Design Space Exploration and Synthesis of CMOS Low Noise Amplifiers

The present work proposes a simple, accurate, fast and exhaustive search procedure for the synthesis of CMOS LNA circuits. The procedure first involves the use of a circuit simulator (Cadence Spectre) to generate a Look Up Table (LUT) containing the device small signal and DC parameters. Then, for a given set of target performance specifications, this LUT is used along with appropriate analytical expressions in a numerical simulator (MATLAB). This will enable one to explore quickly the entire design space to arrive at the optimal values for the device dimensions, bias voltages and bias currents of the LNA circuit. The design methodology is demonstrated by designing Common Gate (CG) LNA and Common Gate Common Source (CGCS) LNA circuits using 0.18μm CMOS UMC technology libraries.