FPGA Based Efficient Fast FIR Algorithm for Higher Order Digital FIR Filter

The scope of the paper is to design a new Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure, which are designed for symmetric coefficients that aim at reducing hardware cost in our design with a constraint that the filter tap must be a multiple of 2. The reduction in area is achieved by replacing the adder by a bulky multiplier. For example, for a 4 parallel 36-tap filter, the proposed structure saves 14 multipliers at the expense of 10 adders, whereas for a four-parallel 288-tap filter, the proposed structure saves 108 multipliers at the expense of 10 adders. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR filter, especially when the length of the filter is very large.