SoC Time to Market Improvement through Device Driver Reuse: An Industrial Experience

With growing complexity of semiconductor devices due to increase in the functionality along with reduced time to market requirements, the semiconductor companies strive to deliver zero defect products and the associated software in short development cycles. In reduced product development cycle customers expect a quality device and reliable software like device drivers, protocol stacks and other middleware package from semiconductor suppliers. The SoC verification infrastructure reuse has the potential to significantly reduce verification cycle time and reduce overall time to market for SoC delivery. In this paper the approach of using the low level software device drivers for front-end SoC functional verification and validation is taken. The same device drivers also run under the customer´s application. This approach enables the verification environment to cover system level scenario testing with the added advantage of checking all possible future issues that may occur at customer end if escaped. In this technique the reusable verification stimulus is written on top of existing Verilog, SystemVerilog verification components and software device drivers. The observed benefits of this technique are reduced time required for setting up simulation and emulation testbench, low level driver validation and ease of stimulus generation for complex scenarios. The advantage with this approach is the early verification of device driver software hence reducing the device driver and related software development cycle time. This methodology led to around 50% reduction in emulation testbench setup time. Initial applications are also enabled on this infrastructure for the customer demos.