New latchup failure mechanism induced by an elevated via resistance on multilayer CMOS technology

A parasitic PNP initiated Vcc latchup failure mechanism was identified as the cause of a blown via contact failure mode. Highly resistive via contacts connecting the underlying N-well substrate to its upper layer Vcc metal bus lines were consistently observed at failing circuits. A defective tungsten (W) plug was determined to be the root cause of the failure mechanism. Based on an established failure model, a circuit simulation was conducted to investigate the impact of via series resistance on latchup triggering current. The contribution of via contact resistance in triggering a latchup mechanism must be considered to maintain high reliability microprocessor products.