A low-jitter distributed synchronous clock using DAC

A low-jitter clock is important to large scale sensors. A new method using low cost DAC, VCXO and FPGA counter to generate distributed synchronous clocks, which is called digital synchronous clock (DDSC), can decrease 60% jitter comparing with traditional PLL (from 36.510 ps down to 14.608 ps). When these two clocks are used as the source of a 24 bit ADC system, the result shows that DDSC makes the total harmonic distortion (THD) increase dramatically (from 106 dB to 117 dB).