Design of radiation tolerant CMOS APS system-on-a-chip image sensors

Author

Eid, El-Sayed ; Ay, Suat U. ; Fossum, Eric R.

Author_Institution

Photobit Technol. Corp., Pasadena, CA, USA

Volume

4

fYear

2002

fDate

2002

Firstpage

38443

Abstract

A methodology for designing radiation tolerant CMOS APS SOC image sensors is presented. It is based on the experimental results of test chips that had been designed, fabricated, and characterized. Details of the basic building blocks of a proposed design are presented. The proposed design is in a 0.35-μm CMOS standard process. The radiation tolerance level could be up to 30 Mrad (Si) total dose of ionizing radiation. The proposed methodology has the potential of yielding highly integrated, highly functional, highly compact, low power, radiation tolerant, cost effective CMOS APS SOC image sensors.

Keywords

CMOS image sensors; adaptive optics; low-power electronics; radiation hardening (electronics); system-on-chip; 0.35 micron; 30 Mrad; APS; CMOS image sensors; active pixel sensors; low power; radiation tolerance level; radiation tolerant CMOS; system-on-a-chip; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS image sensors; CMOS process; CMOS technology; Charge coupled devices; Image sensors; Integrated circuit technology; Space technology; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace Conference Proceedings, 2002. IEEE

Print_ISBN

0-7803-7231-X

Type

conf

DOI

10.1109/AERO.2002.1036912

Filename

1036912