• DocumentCode
    2309859
  • Title

    The digital algorithm processors for the ATLAS Level-1 Calorimeter Trigger

  • Author

    Silverstein, S.B.

  • Author_Institution
    Dept. of Phys., Stockholm Univ., Stockholm, Sweden
  • fYear
    2009
  • fDate
    10-15 May 2009
  • Firstpage
    334
  • Lastpage
    342
  • Abstract
    The ATLAS Level-1 Calorimeter Trigger identifies high-ET jets, electrons/photons and hadrons, and measures total and missing transverse energy in proton-proton collisions at the Large Hadron Collider. Two subsystems-the Jet/Energy-sum Processor (JEP) and the Cluster Processor (CP)-process data from every crossing, and report feature multiplicities and energy sums to the ATLAS Central Trigger Processor, which produces a Level-1 Accept decision. Locations and types of identified features are read out to the Level-2 Trigger as regions-of-interest, and quality-monitoring information is read out to the ATLAS data acquisition system. The JEP and CP subsystems share a great deal of common infrastructure, including a custom backplane, several common hardware modules, and readout hardware. Some of the common modules use FPGAs with selectable firmware configurations based on their location in the system. This approach saved substantial development effort and provided a uniform model for firmware and software development. We present an in-depth description of the two subsystems as manufactured and installed. We compare and contrast the JEP and CP systems, and discuss experiences during production, installation and commissioning. We also briefly present results of recent tests that suggest an interesting upgrade path for higher luminosity running at the LHC.
  • Keywords
    data acquisition; electron detection; high energy physics instrumentation computing; particle calorimetry; position sensitive particle detectors; ATLAS central trigger processor; ATLAS data acquisition system; ATLAS level-1 calorimeter trigger; LHC; Large Hadron Collider; cluster processor-process data; digital algorithm processor; electron-photons; hadrons; hardware modules; high-ET jet; jet-energy-sum processor; proton-proton collision; readout hardware; Backplanes; Clustering algorithms; Data acquisition; Electrons; Energy measurement; Field programmable gate arrays; Hardware; Large Hadron Collider; Microprogramming; Photon collider; first-level trigger; level-1; parallel architectures; pipeline processing; programmable gate arrays; real-time systems; triggering;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real Time Conference, 2009. RT '09. 16th IEEE-NPSS
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-4454-0
  • Type

    conf

  • DOI
    10.1109/RTC.2009.5321731
  • Filename
    5321731