Title :
Reduction in Parasitic Capacitances for Transmission Gate with the Help of CPL
Author :
Srivastava, Viranjay M. ; Patel, Rachit ; Parashar, Harpreet ; Singh, G.
Author_Institution :
Electron. & Commun. Eng. Dept., Jaypee Univ. of Inf. Technol., Solan, India
Abstract :
Elimination of the p-MOS transistor from the pass gate network significantly reduces the parasitic capacitances associated with each node in the circuit, thus, the operation speed is typically higher as compared to the CMOS counterpart. But then the improvement in the transient characteristics comes at the price of increased process complexity. In Complementary pass transistor logic (CPL) circuit, the threshold voltage of the n-MOS transistors in the pass gate network must be reduced to about the zero voltage through threshold adjustments implants in order to eliminate the threshold voltage drop. Thus on the other hand reduces the overall noise immunity and makes the transistor more susceptible to sub threshold conduction in the off mode. Presented CPL design style is highly modular as a wide range of function can be realized by using this basic pass transistor structure.
Keywords :
CMOS integrated circuits; CMOS logic circuits; MOSFET; logic gates; CMOS counterpart; complementary pass transistor logic circuit; n-MOS transistors; p-MOS transistor; parasitic capacitance reduction; transmission gate; zero voltage; CMOS logic circuits; Delay; Logic circuits; Logic design; Logic devices; Parasitic capacitance; Power dissipation; Threshold voltage; Throughput; Very large scale integration; CPL; Delay time; Parasitic capacitance; Power dissipation; Speed performance of gate; VLSI; transmission gate;
Conference_Titel :
Recent Trends in Information, Telecommunication and Computing (ITC), 2010 International Conference on
Conference_Location :
Kochi, Kerala
Print_ISBN :
978-1-4244-5956-8
DOI :
10.1109/ITC.2010.67
