High density central I/O circuits for CMOS

An I/O circuit design technique for VLSI CMOS which reduces the percentage of chip area occupied by I/O circuits from the typical 16% to 30% range to less than 3% for a 256 I/O chip is described. The percentage of chip area occupied per I/O is reduced from the typical 0.07% to 0.23% range to only 0.01%. In this high-density I/O design technique, I/O circuits are grouped into stackable macros and placed in the central area of the chip. The top metal layer, wires the I/O circuits to the package connections. The I/O area savings are achieved through shared guard rings, elimination of reserved I/O area, and integration of the ESD (electrostatic discharge) protection and transmission line clamping into the I/O devices themselves