Full Subtractor Circuit Design with Independent Double Gate Transistor

Circuit with double gates using independently controlled gates have been proposed to reduce the number of gates and to increase the logic densities per area. This paper introduces a vertical slit FET (double gate transistor) which has been demonstrated with the help of figures with unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits. The impact on figure of merit for power consumption, delay, leakage behavior and area of fabricated devices are presented. A new subtractor is proposed where the power and area could be reduced as compared with a tied gate configuration. With the help of double gate transistor, some of the used parameters value has been varied significantly thus improving its performance quality. Double gate transistor circuit is the first choice for low power application domain.