Efficient integer implementations for faster linear transforms

Author

Trelewicz, J.Q. ; Brady, Michael I. ; Mitchell, Joan L.

Author_Institution

IBM Almaden Res. Center, San Jose, CA, USA

Volume

2

fYear

2001

fDate

4-7 Nov. 2001

Firstpage

1161

Abstract

Higher throughput requirements in image processing systems require faster implementations of the underlying transforms. A new architecture for efficient implementations of linear, orthogonal transforms is discussed, with specific examples developed for the 2-D DCT in image compression. It is shown that the methods described in this paper can provide lower real estate usage in FPGAs by as much as 3-4 /spl times/, as well as reduction in execution cycles by about 30 % on a range of embedded processors where more clock cycles are required for multiplication than for addition.

Keywords

data compression; digital arithmetic; discrete cosine transforms; embedded systems; field programmable gate arrays; image coding; transform coding; 2D DCT; FPGA real estate usage; addition operation; clock cycles; discrete cosine transforms; embedded processor execution cycles; image compression; image processing systems; integer implementation architecture; linear orthogonal transforms; multiplication operation; Clocks; Discrete cosine transforms; Field programmable gate arrays; Image analysis; Image processing; Performance analysis; Printing; Signal analysis; Table lookup; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-7147-X

Type

conf

DOI

10.1109/ACSSC.2001.987674

Filename

987674