Fast control system in BESIII experiment

This paper describes the fast control and clock distribution system of BESIII experiment. The function of this system is transmitting fast control signals from trigger system to front-end electronics and readout electronics, receiving status signals from readout electronics for trigger system, and distributing system clock to trigger, front-end and readout electronics. The fast control signals include system reset, SEDES reset, L1 pass, L1 check, FPGA reload, readout Error, Full in readout buffer and others. These signals are transmitted in serial way and by optical fibers so that a good isolation between front-end electronics and trigger system is achieved to prevent from loop current interference. Special treatment is made to prevent from the timing uncertainty in the deserialization. The system has been put in operation for a year with good reliability and stability.