DocumentCode
2310986
Title
CDMA as a multiprocessor interconnect strategy
Author
Bell, Robert H., Jr. ; Kang, Chang Yong ; John, Lizy ; Swartzlander, Earl E., Jr.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Volume
2
fYear
2001
fDate
4-7 Nov. 2001
Firstpage
1246
Abstract
A binary CDMA bus is proposed as a communications interconnect for multiprocessor systems. The binary CDMA bus is a digital bus which incorporates spread-spectrum technology to encode multiple data streams in parallel onto the same physical interconnect. Mean value analysis is used to show that, for resource bandwidth-limited applications, the binary CDMA bus can deliver a throughput speedup over a split-transaction bus as large numbers of processors are interconnected, giving more scalable performance without additional end-to-end physical bus links. By monitoring bus utilization, the binary CDMA bus can be dynamically activated to alleviate contention and queueing delays experienced by a conventional bus. The inherently parallel access of the bus makes it useful for streaming data in DSP applications.
Keywords
code division multiple access; delays; multiprocessing systems; multiprocessor interconnection networks; queueing theory; spread spectrum communication; DSP applications; binary CDMA bus; communications interconnect; contention delays; data streaming; mean value analysis; multiprocessor interconnect strategy; queueing delays; spread-spectrum technology; Delay; Digital signal processing; File servers; Integrated circuit interconnections; LAN interconnection; Monitoring; Multiaccess communication; Multiprocessing systems; Protocols; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-7147-X
Type
conf
DOI
10.1109/ACSSC.2001.987690
Filename
987690
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