Characterizing jitter performance of multi gigabit FPGA-embedded serial transceivers

High-speed serial links are a key component of data acquisition systems for High Energy Physics. They carry physics events data and often also clock, trigger and fast control signals. For the latter applications, the jitter on the clock recovered from the serial stream is a critical parameter since it directly affects the timing performance of data acquisition and trigger systems. Latest Field Programmable Gate Arrays (FPGAs) include multigigabit serial transceivers, which are configurable with various options and support many data encodings. However, an in-depth jitter characterization of those devices is not available yet. In this paper we present measurements of the jitter on the clock recovered by a GTP transceiver (embedded in a Xilinx Virtex 5 FPGA) as a function of the data pattern, coding and logic activity on the transmitter and receiver FPGAs.