FIR filter design program that matches specifications rather than filter coefficients results in large savings in FPGA resources

The standard FIR filter design approach which uses ideal filter coefficients determined by a filter design algorithm such as remez exchange, windowing, or similar techniques, rounding or truncating the ideal coefficients to a specific number of bits and realizing the digital filter using one of the standard FIR filter structures generates filters with considerably more hardware than is required to meet the original specifications. By using a new public-domain computer program written in Matlab, FIR filters can be designed with one-third of the hardware required using standard techniques. In a typical filter example described by the Xilinx application notes, an 8-tap FIR filter can be reduced using the CSD/DM technique from 584 slices to only 186 slices for Synplify Pro 6.0 and from 645 slices to only 214 slices for FPGA express 3.4.