Design of power-optimal buffers tunable to process variability

In many digital designs, multi-stage tapered buffers are needed to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this paper, we propose two novel tunable buffer designs that enable power reduction in the presence of process variation. A strategy to derive the optimal buffer size and tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variation. Using a combination of HSPICE simulations and our optimization algorithm, we show that up to 30% average power reduction can be achieved with the proposed buffer structures.