Wafer burn-in (WBI) technology for RAM´s

Author

Furuyama, T. ; Kushiyama, N. ; Noji, H. ; Kataoka, M. ; Yoshida, T. ; Doi, S. ; Ezawa, M. ; Watanabe, T.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

639

Lastpage

642

Abstract

A simple and practical wafer burn-in (WBI) technology is described. This technology effectively screens reliability failures of random access memories on a wafer, prior to die-sorting. As a result, obtaining "known-good" RAM chips becomes much more realistic. Since most of the failures occurred during the WBI can be replaced by spare rows or columns, the product yield improves. The new WBI technology uses the conventional wafer prober and multi-chip probe card environment, and does not need any additional process steps which previous WBI proposals required.<>

Keywords

DRAM chips; SRAM chips; circuit reliability; failure analysis; integrated circuit technology; integrated circuit testing; RAM chips; RAM testing; multichip probe card environment; product yield improvement; random access memories; reliability failure screening; wafer burn-in technology; wafer prober; Assembly; Capacitors; Circuit testing; Costs; Dielectric substrates; Microelectronics; Production; Random access memory; Sorting; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347230

Filename

347230