Electrothermal simulation of electrical overstress in advanced nMOS ESD I/O protection devices

Author

Diaz, C.H. ; Duvvury, C. ; Sung-Mo Kang

Author_Institution

Div. of Integrated Circuits Bus., Hewlett-Packard Co., Palo Alto, CA, USA

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

899

Lastpage

902

Abstract

For electrical overstress (EOS) and electrostatic discharge (ESD) reliability of submicron ICs, there are currently no available accurate circuit-level simulation tools to analyze and design input/output protection devices. In this paper, we introduce a unique circuit-level electrothermal simulator that can accurately predict the protection device behaviour up to the onset of second breakdown under high-current stress events. The results shown here demonstrate practical application to EOS/ESD robustness in sub-micron technologies.<>

Keywords

MOS integrated circuits; circuit analysis computing; circuit reliability; electrostatic discharge; protection; EOS/ESD; circuit-level electrothermal simulator; electrical overstress; electrostatic discharge; high-current stress; nMOS input/output protection devices; reliability; second breakdown; submicron ICs; Analytical models; Circuit simulation; Discrete event simulation; Earth Observing System; Electrostatic analysis; Electrostatic discharge; Electrothermal effects; MOS devices; Predictive models; Protection;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347255

Filename

347255