Oxide thickness dependence of inverter delay and device reliability for 0.25 /spl mu/m CMOS technology

We investigate the tradeoffs and optimisation of gate oxide thickness and power supply voltage for a high-performance nominal 0.25 /spl mu/m gate length CMOS technology and evaluate the reliability design constraints in terms of time-dependent-dielectric breakdown (TDDB), channel-hot-electrons (CHE), and gate-induced-drain leakage. Thinner t/sub ox/ allows higher operating oxide field, higher CHE lifetime, and higher resistance to D/sub it/ generation. An optimal t/sub ox/ exists for a minimal t/sub delay/ (inverter chain delay) with bounds on maximum allowable V/sub DD/ at a given t/sub ox/ determined by CHE lifetime (for thicker t/sub ox/) and by TDDB lifetime (for thinner t/sub ox/). For low inverter fanout FO=1, a minimum t/sub delay/ for our experimental conditions occurs with t/sub ox/=68 /spl Aring/ and V/sub DD/=2.7 V. For higher FO/spl ges/5, a minimum t/sub delay/ occurs for thicker t/sub ox/=88 /spl Aring/ and with V/sub DD/=2.5 V.<>