• DocumentCode
    2313041
  • Title

    The improvement of delaminating at interface between molding compound and Gold substrate bond pad in BGA(ball grid array) package

  • Author

    Hsieh, Chin Chun ; Shih, Ming Chang ; Lan, W.H.

  • Author_Institution
    ASE, Kaohsiung, Taiwan
  • fYear
    2010
  • fDate
    20-22 Oct. 2010
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    The miniaturization and increasing complex integration of functional chips handheld devices such as cellular phones have led to the widespread adoption of chip scale packages (CSPs) and ball grid array (BGA) packages. Lighter weight, thinner thickness, smaller size, high I/O pins, low cost, high functions, high quality and green environmental material are trend of IC packages and continuously challenge manufacturer and material supplier to develop new technologies and new materials to meet the process requirements in packaging. Ball-grid arrays (BGA) packages which place output pins in the form of a solder ball matrix provides effective solutions for high capacity interconnections and efficient thermal management of the power ICs. The I/O connections of the BGA are generally fabricated on laminated substrates (BT-based) or polyimide-based films. Therefore, the entire area of substrate can be used to reroute the interconnection. BGA has the advantage of lower ground or power inductance thereby assigning ground or power nets via a shorter current path to PCB. The higher functional capabilities of the BGA package technology benefit high power and high speed ICs that require enhanced electrical and thermal performance. However, in BGA packaging the issue of delaminating between molding compound and wire bonding pad on the ENEPG (Electroless Ni Eletroless Pd immerse Gold) substrate after product pre-con test has been an issue to liability test defined by Joint Electron Device Engineering Council (JEDEC).
  • Keywords
    ball grid arrays; bonding processes; chip scale packaging; delamination; gold alloys; integrated circuit interconnections; laminates; matrix algebra; moulding; power integrated circuits; substrates; thermal management (packaging); BGA package; CSP; ENEPG; I/O connections; IC packages; JEDEC; Joint Electron Device Engineering Council; ball grid array package; cellular phones; chip scale packages; complex integration; delamination; electrical performance; electroless nickel electroless palladium immerse gold substrate; functional chips handheld devices; gold substrate bond pad; green environmental material; high capacity interconnections; high power IC; high speed IC; interface; laminated substrates; liability test; miniaturization; molding compound; polyimide-based films; power inductance; power nets; solder ball matrix; thermal management; thermal performance; wire bonding pad; Bonding; Compounds; Delamination; Gold; Substrates; Surface treatment;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th International
  • Conference_Location
    Taipei
  • ISSN
    2150-5934
  • Print_ISBN
    978-1-4244-9783-6
  • Electronic_ISBN
    2150-5934
  • Type

    conf

  • DOI
    10.1109/IMPACT.2010.5699601
  • Filename
    5699601