Title :
Novel elevated silicide source/drain (ESSOD) by load-lock LPCVD-Si and advanced silicidation processing
Author :
Kotaki, H. ; Nakano, M. ; Takegawa, Y. ; Kakimoto, S. ; Mori, Y. ; Mitsuhashi, K. ; Takagi, J. ; Tsuchimoto, S. ; Akagi, Y.
Author_Institution :
Central Res. Labs., Sharp Corp., Nara, Japan
Abstract :
The Si epitaxial growth layer on the active region was formed selectively under the low temperature condition of 620/spl deg/C without a conventional SEG system. This technology was achieved using the conventional low-temperature "Load-Lock LPCVD-Si" deposition system and selective etching with HNO/sub 3/, CH/sub 3/COOH and HF based solutions. Low resistive and low leakage shallow n/sup +p and p/sup +n junctions were realized by the E_levated S_ilicide So_urce/D_rain (ESSOD) structure using this technology. Furthermore, contact resistances of about 2.0/spl sim/3.O/spl Omega/ were obtained for 0.35/spl mu/m diameter with A_l-plug/c_ollimated Ti/TiN/Ti/T_i-silicide/e_pitaxial-Si c_ontact (ACTEC) structure on both n/sup +/- and p/sup +/-ESSOD regions.<>
Keywords :
contact resistance; elemental semiconductors; etching; p-n homojunctions; semiconductor epitaxial layers; semiconductor growth; silicon; vapour phase epitaxial growth; 620 C; ACTEC; Al-Ti-TiN-Ti-TiSi-Si; Al-plug/collimated Ti/TiN/Ti/Ti-silicide/epitaxial-Si contact; ESSOD; HF; HNO/sub 3/; Si epitaxial growth; contact resistances; elevated silicide source/drain; ethanol; load-lock LPCVD-Si; low temperature; selective etching; shallow n/sup +p junctions; shallow p/sup +n junctions; silicidation processing; CMOS technology; Collimators; Epitaxial growth; Etching; Hafnium; MOSFETs; Silicidation; Silicides; Temperature; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347269
