Title :
A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs
Author :
Ikeda, S. ; Asayama, K. ; Hashimoto, N. ; Fujita, E. ; Yoshida, Y. ; Koike, A. ; Yamanaka, T. ; Ishibashi, K. ; Meguro, S.
Author_Institution :
Div. of Semicond. & Integrated Circuit, Hitachi Ltd., Tokyo, Japan
Abstract :
Stacked Split Word-Line cell technology suitable for low voltage operation, large capacity and high speed SRAMs has been proposed. Two pull-down transistors and two access transistors are fabricated employing two separate gate formations. A pair of split word-lines is stacked over pull-down transistors. That permits large cell ratio in small cell area and independent optimization of pull-down and access transistors. Threshold voltage of access transistors is lowered to improve cell stability. Top gate thin film polysilicon transistor and Vcc plate are used to make cell node capacitor and improve soft error immunity. This technology is applied to a fast 16M bit SRAM and enabled a 7.16 /spl mu/m/sup 2/ cell area in relaxed 0.4 /spl mu/m layout rule utilizing conventional i-line stepper without phase-shift masks.<>
Keywords :
MOS integrated circuits; SRAM chips; VLSI; cellular arrays; photolithography; thin film transistors; 0.4 micron; 16 Mbit; access transistors; cell area; cell node capacitor; cell ratio; cell stability; gate formations; high speed SRAMs; i-line stepper; large capacity memories; layout rule; low-voltage operation; pull-down transistors; soft error immunity; stacked split word-line cell; threshold voltage; top gate thin film polysilicon transistor; Capacitors; Etching; Oxidation; Plasma applications; Plasma measurements; Random access memory; Rough surfaces; Silicon; Surface roughness; Thin film transistors;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347276
