Title :
A newly designed planar stacked capacitor cell with high dielectric constant film for 256 Mbit DRAM
Author :
Eimori, T. ; Ohno, Y. ; Kimura, H. ; Matsufusa, J. ; Kishimura, S. ; Yoshida, A. ; Sumitani, H. ; Maruyama, T. ; Hayashide, Y. ; Moriizumi, K. ; Katayama, T. ; Asakura, M. ; Horikawa, T. ; Shibano, T. ; Itoh, H. ; Sato, K. ; Namba, K. ; Nishimura, T. ; Sa
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
Thin film of (Ba/sub 0.75/Sr/sub 0.25/)TiO/sub 3/ with equivalent SiO/sub 2/ thickness of 0.47 nm has been developed for capacitor dielectric film of 256 Mbit DRAM. A novel cell design named FOGOS (FOlded Global and Open Segment bit-line cell) structure is also proposed for 256 Mbit DRAM. By combining high dielectric constant film and FOGOS design, we have succeeded in making a practical and integrated cell that has sufficient cell capacitance with planar stacked capacitor, small bitline parasitic capacitance and large lithographic tolerance of alignment and DOF. 0.72 /spl mu/m/sup 2/ cell size based on 0.25 /spl mu/m process technology is realized.<>
Keywords :
DRAM chips; VLSI; barium compounds; dielectric thin films; integrated circuit technology; permittivity; strontium compounds; (Ba/sub 0.75/Sr/sub 0.25/)TiO/sub 3/; 0.25 micron; 0.47 nm; 256 Mbit; BaTiO/sub 3/SrTiO/sub 3/; DRAM; FOGOS; bitline parasitic capacitance; capacitor dielectric film; cell capacitance; cell design; dielectric constant; dielectric thin film; folded global and open segment bit-line cell; lithographic tolerance; planar stacked capacitor cell; process technology; Binary search trees; Capacitance; Capacitors; Dielectric films; Dielectric thin films; High-K gate dielectrics; Leakage current; Random access memory; Substrates; Temperature;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347281
