Title :
A 0.6 /spl mu/m/sup 2/ 256 Mb trench DRAM cell with self-aligned BuriEd STrap (BEST)
Author :
Nesbit, L. ; Alsmeier, J. ; Chen, B. ; DeBrosse, J. ; Faheyk, P. ; Gall, M. ; Gambino, J. ; Gernhard, S. ; Ishiuchi, H. ; Kleinhenz, R. ; Mandelman, J. ; Mii, T. ; Morikado, M. ; Nitayama, A. ; Parke, S. ; Wong, H. ; Bronner, G.
Author_Institution :
Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA
Abstract :
In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd STrap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605/spl mu/m/sup 2/ at 0.25 /spl mu/m design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells. The BEST cell concept, process, and design, as well as preliminary results obtained from a 256 Mb DRAM development test chip, processed with optical lithography down to 0.25 /spl mu/m design rules, are presented in this paper.<>
Keywords :
DRAM chips; VLSI; cellular arrays; field effect integrated circuits; integrated circuit technology; photolithography; 0.25 micron; 256 Mbit; BEST; design rules; folded bitline cell; optical lithography; self-aligned buried strap; trench DRAM cell; Capacitors; Dielectric substrates; Etching; Fuses; Implants; Metal-insulator structures; Oxidation; Random access memory; Semiconductor films; Silicon;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347282
