Fast and Efficient On-Chip Interconnection Delay Modeling for High Speed VLSI Systems

Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed ICpsilas. This paper presents an closed-form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. This analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of this analytical models is several orders of magnitude faster than simulation using SPICE.