Three dimensional interconnects with through silicon vias and electroplating solder microbumps

Since 3D-IC becomes popular nowadays, solder micro-bumps plays an important role to develop TSV technology. This study verifies solder micro-bump efficiency via cracking as index. The micro-bump cracking is observed at the interface of intermetallic compound (IMC) layer after Si chip and Si carrier bonding. It was found that P-rich Ni layer will perform weaker and brittle solder joint by means of EDS. Figure 1 shows the cross section schematic drawing as 3D chip stacking for a Si chip and a Si carrier. The solder micro-bumps and under bump metallurgy (UBM) pads are fabricated on the Si chip and the top side of Si carrier respectively. The TSVs in Si carrier functions as interconnects. After flip chip assembled Si chip and Si carrier, the whole assembly is joint onto a bismaleimide triazine (BT) substrate with redistribution layer and solder joints through by bottom of Si carrier. In this study, the Si carrier was patterned with the diameter and depth by 50um and 120um respectively at room temperature with BOSCH process. The smoother scallop was achieved below 150nm. Excellent passivation step coverage for 39% ≃ 50% from via top to bottom side was also obtained. TSV formation processed by electroplating Cu and X-ray result shows void free in TSV. After TSV formation, the electrical nickel and immersion gold (ENIG) was used for the UBM. The total thickness of 50μm Ni/Cu and Sn/Ag solder micro bumps were fabricated by electroplating on top of Si chip.