Title :
Timing optimizations in a high-level synthesis system
Author :
Gupta, Gopal ; Pastorello, Douglas ; House, Glenn
Author_Institution :
Silc Technol. Inc., Burlington, MA, USA
Abstract :
Two alternative techniques for meeting tight timing constraints on a network, fanout compensation and resource rearchitecting, are discussed, and it is shown how these can be used together to obviate the need for expensive logic optimization steps in some cases. Both these techniques have been successfully used in SilcSyn, an ASIC design synthesis system from Silc Technologies. All techniques presented are targeted towards systems that synthesize designs in standard cell or gate array libraries
Keywords :
VLSI; circuit layout CAD; logic CAD; logic arrays; optimisation; ASIC design synthesis system; Silc Technologies; SilcSyn; fanout compensation; gate array libraries; high-level synthesis system; meeting tight timing constraints; resource rearchitecting; standard cell libraries; timing optimisation; Aging; Application specific integrated circuits; Arithmetic; Constraint optimization; Control system synthesis; High level synthesis; Libraries; Logic; Network synthesis; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124732
