Low Power Tiered Wake-up Module for Lightweight Embedded Systems Using Cross Correlation

A major objective in design of wearable and light-weight embedded systems is reducing the power consumption. This leads to reduction of the battery size and enhances the wear ability of the system. In this paper, we propose an ultra low power tiered wake-up architecture with signal processing capability. The signal processing is based on template matching and normalized cross correlation. The template matching at the beginning is performed with low sensitivity (with fewer bits and samples) but at very low power. Initial template matching removes signals that are obviously not of interest. If the signal is likely to be of interest, the sensitivity and the power consumption of the template matching blocks are gradually increased, until the signal of interest is detected with a reasonable confidence. Consequently, a microcontroller is activated for additional processing. The tunable parameters for template matching include the number of samples, the size of template (window size) and the number of bits per sample. The proposed architecture can enable the next generation of ultra low power or even battery less wearable and implantable computers due to tremendously reducing the power consumption of the signal processing. We estimate that the power consumption of the proposed tiered wake-up circuitry will be three to six orders of magnitude smaller than state-of-the-art low power microcontrollers, depending on the complexity of the template matching. Further, the proposed architecture provides high level of programmability which is lacking in ASIC architectures custom built for applications.