Improving gate oxide integrity in p/sup +/pMOSFET by using large grain size polysilicon gate

Author

Koda, M. ; Shida, Y. ; Kawaguchi, J. ; Kaneko, Y.

Author_Institution

Div. of Tech. Res., Kawasaki Steel Corp., Chiba, Japan

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

471

Lastpage

474

Abstract

The effect of polysilicon grain size on the gate oxide integrity in p/sup +/pMOS devices was investigated by measuring the electrical characteristics of a MOS capacitor. Good gate oxide integrity was never obtained when using conventional polysilicon with a small (/spl sim/0.05 /spl mu/m) grain size. We report for the first time use of large (/spl sim/1.0 /spl mu/m) grain size polysilicon to solve this problem for gate oxide quality. Additionally, in large-grain-size polysilicon, the efficiency of boron activation was increased and boron diffusion through the gate oxide into the channel region was strongly suppressed.<>

Keywords

boron; dielectric thin films; electric breakdown of solids; grain size; insulated gate field effect transistors; silicon; 1 micron; B activation; B diffusion suppression; MOS capacitor; PMOS transistor; Si-SiO/sub 2/; electrical characteristics; gate oxide integrity improvement; large grain size polysilicon; p/sup +/-pMOSFET; polysilicon gate; Annealing; Boron; Electric breakdown; Grain size; Large scale integration; MOS capacitors; MOSFET circuits; Semiconductor films; Silicon; Size control;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347308

Filename

347308