Algorithm for high speed shared radix 8 division and radix 8 square root

An algorithm for performing radix-8 division and square root in a shared hardware is described. To achieve short iteration cycle time, it utilizes an optimized `next quotient/root prediction PLA´ generally used in a radix-4 SRT division with minimal redundancy. In addition, the partial remainder, partial radicand, quotient, and root are generated and saved in redundant forms, thereby eliminating the slow-carry look-ahead adder from the critical path timing of the iteration cycle. This method successfully avoids the need to generate nontrivial divisor/root multiples (3x, 5x, etc.) and also avoids the complex radix-8 next quotient prediction PLA typically used in a conventional radix-8 SRT division. It also shows that a significant amount of hardware sharing can be achieved when square root and division are performed at the same radix