Real area-power-delay trade-off in EUCLID logic synthesis system

The EUCLID logic synthesis system, in which true area-power-delay trade-off is possible, is described. To achieve this, area, delay, and power consumption are estimated at every stage of the process, and optimization decisions taken accordingly. Optimal gate-sizing fine tunes the delay of the circuit, EUCLID provides a framework to explore the area-delay-power design space for a given circuit, giving the designer an optimal implementation based on design needs. Currently, EUCLID is able to handle circuits of several thousands of transistors, with each tool running in a few minutes. Smaller circuits, with smaller hundreds of transistors, only take seconds to run