Thin CVD stacked gate dielectric for ULSI technology

In this paper we have presented an overview of CVD stacked gate dielectrics and specific results which show the advantages of this approach. A gate dielectric with low defect density and high charge-to-breakdown can be achieved by the CVD stacked structure. This gate dielectric process has a stronger resistance to metal contamination. The stacked gate oxide reduces the gate oxide thinning problem at the field oxide edge for both poly buffer LOCOS (PBL) and trench isolation. It improves the charge-to-breakdown value for a manufacturable dry/dry etch process for the nitride/poly mask used for PBL isolation. The stacked gate oxide shows a stronger resistance to the increased potential caused by magnetic field during poly gate etch. Finally, the oxynitride/CVD stacked dielectric further improves the charge-to-breakdown under plasma etch process for nitride/poly mask removal.<>