Verification of the CoreNet Fabric with SystemVerilog

The Freescale QorIQ¿ communication platforms are system-on-chip (SoC) processors containing single, dual and many cores and enable the next era of networking by offering advanced levels of performance, power-efficiency and programmability. The QorIQ P4080 communications processor, the signature member of the product line, integrates eight enhanced Freescale Power Architecture^® processors, a tri-level cache hierarchy, and innovative high-speed CoreNet¿ fabric and data path acceleration. The CoreNet fabric is an interconnect architecture suitable for scalable on-chip network to connect multiple Power Architecture processing cores with caches, stand-alone caches and memory subsystems. The CoreNet fabric was designed to provide a coherent multicore migration solution enabling the move to multicore. This paper focuses on the verification challenges and solutions associated with verifying the CoreNet platform using SystemVerilog (SV).