An ultra low power lateral bipolar polysilicon emitter technology on SOI

Author

Dekker, R. ; van der Einden, W.T.A. ; Maas, H.G.R.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

75

Lastpage

78

Abstract

Until now the lateral bipolar transistor on SOI has been presented as an option in a CMOS process. In this investigation we show that this device structure is also very attractive for purely bipolar applications, enabling high frequency operation at ultra low power levels. Excellent devices with emitter areas down to 0.15 /spl mu/m/sup 2/, with scaled junction capacitances and f/sub T/ as high as 15 GHz are demonstrated. Due to the properly scaled junction capacitances a f/sub max/ of 15 GHz is realised at collector currents as low as 15 /spl mu/A.<>

Keywords

bipolar integrated circuits; integrated circuit technology; semiconductor-insulator boundaries; silicon; 15 GHz; 15 muA; SOI; Si; collector currents; cut off frequency; emitter areas; high frequency operation; lateral bipolar transistor; polysilicon emitter technology; scaled junction capacitances; ultra low power; Anisotropic magnetoresistance; Bipolar transistors; CMOS technology; Capacitance; Etching; Fabrication; Frequency; Laboratories; Resists; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347395

Filename

347395