Title :
15-ps ECL/74-GHz f/sub T/ Si bipolar technology
Author :
Uchino, T. ; Shiba, T. ; Kikuchi, T. ; Tamaki, Y. ; Watanabe, A. ; Kiyota, Y. ; Honda, M.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A very high performance Si bipolar transistor technology has been developed. In-situ phosphorus doped polysilicon (IDP) emitter technology was used to reduce the thermal budget and emitter resistance. Very thin bases were obtained by rapid vapor-phase doping (RVD) and low energy BF2/sup +/ ion implantation. Double-polysilicon self-aligned bipolar technology with U-groove isolation on bonded SOI wafers was used to reduce the parasitic capacitances. Using these key techniques, a minimum ECL gate delay time of 15 ps and a cut-off frequency of 74 GHz have been achieved.<>
Keywords :
bipolar integrated circuits; bipolar transistors; elemental semiconductors; emitter-coupled logic; integrated logic circuits; ion implantation; semiconductor doping; silicon; 15 ps; 74 GHz; ECL gate delay time; Si bipolar transistor technology; Si:P-Si:BF/sub 2/; U-groove isolation; bonded SOI wafers; cut-off frequency; double-polysilicon self-aligned technology; emitter resistance; in-situ phosphorus doped polysilicon emitter; low energy BF2/sup +/ ion implantation; parasitic capacitances; rapid vapor-phase doping; thermal budget; Circuit optimization; Current density; Delay; Epitaxial layers; Grain size; Impurities; Logic devices; Plugs; Ring oscillators; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347397
