Ultra-thin TiN/Ta/sub 2/O/sub 5W capacitor technology for 1 Gbit DRAM

Author

Kamiyama, S. ; Suzuki, H. ; Watanabe, H. ; Sakai, A. ; Oshida, M. ; Tatsumi, T. ; Tanigawa, T. ; Kasai, N. ; Ishitani, A.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

49

Lastpage

52

Abstract

A highly reliable Ta/sub 2/O/sub 5/ (1.6 nm SiO/sub 2/ equivalent thickness) capacitor with TiN/Ta/sub 2/O/sub 5/W structure is developed for 1 Gbit DRAMs. This Ta/sub 2/O/sub 5/ capacitor formed on the enlarged area electrode achieves a cell capacitance of 30 fF with 0.6 /spl mu/m-height storage-node in a area of 0.24 /spl mu/m/sup 2/. The critical steps in this technology are using of tungsten (W) for the storage-node surface, oxygen-plasma annealing after Ta/sub 2/O/sub 5/ film deposition, and a hemi-spherical grained (HSG) Si before W film deposition. This 1.6 nm SiO/sub 2/ equivalent thick Ta/sub 2/O/sub 5/ capacitor on HSG Si structure is realized at half of 1.5 V operation voltage with 10/sup -8/A/cm/sup 2/ leakage current density.<>

Keywords

DRAM chips; annealing; integrated circuit technology; metal-insulator-semiconductor devices; 1 Gbit; 1.5 V; 30 fF; DRAM; Si; TiN-Ta/sub 2/O/sub 5/-W; cell capacitance; enlarged area electrode; hemi-spherical grained Si; leakage current density; oxygen-plasma annealing; storage-node surface; ultra-thin TiN/Ta/sub 2/O/sub 5W capacitor technology; Annealing; Capacitance; Capacitors; Dielectric measurements; Electrodes; Leakage current; Pollution measurement; Random access memory; Semiconductor films; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347401

Filename

347401